An active matrix substrate has been used in, for example, a liquid crystal display and an organic EL (electro luminescent) display. This active matrix substrate conventionally includes metal wiring, such as signal lines and scanning lines, and pixel electrodes. The metal wiring and the pixel electrodes are generally formed as follows. Namely, a metal thin film is formed by carrying out a spattering method using a metal target, or an evaporation method. On this metal thin film, a mask is formed by carrying out a photolithography. Then, a desirable pattern of the metal wiring and the pixel electrodes are formed by carrying out a dry etching or a wet etching with respect to the mask.
A film thickness of the metal thin film, from which the metal wiring or the pixel electrode is formed, is found based on (i) a pattern which is specified by a width of the wiring or the like to be formed and (ii) a required resistance value. An entire thickness of the entire metal thin film is determined in accordance with a region which requires the most thickness.
Now it is possible to form, on the periphery of the active matrix substrate, driver elements or elements each having a part of function of the driver element so that the active matrix substrate and the elements are integral with each other. This is attributed to recent improvements in a technology for switching element, such as a poly silicon TFT or the like. In this case, a resistance value required in the metal wiring for supplying power and a signal or the like to these elements is lower than that required in a conventional signal line and scanning line.
Further, in an active matrix substrate, adopting an external driving method, such as TAB (Tape Automated Bonding) and COG (Chip On Glass), the active matrix substrate is provided with wiring for use in transmitting signals between TAB chips, or COG chips. This simplifies an external circuit board. Due to an increase in a size of a display in recent years, it is necessary, in many cases, that this wiring also have a lower resistance value than that required in the conventional signal line and scanning line.
In order to reduce the resistance of wiring and a terminal which require a low resistance as mentioned above, each of the wiring and the terminal may be provided thereon or thereunder with an auxiliary metallic member. The following describes examples of a method for using a metal material entirely or partially in the wiring or the terminal.
Firstly, there is a method in which an Ni film or the like is provided. This Ni film or the like will serve as (i) metal for facilitating growth of a plated film to become foundation wiring for plated wiring, or (ii) metal for improving adhesiveness with respect to deposited metal. Further, there is a method in which Ti or the like is provided to serve as metal for improving (i) an electric contact with a semiconductor and/or heterogeneous metal, and/or (ii) adhesiveness needed in a formation of a metallic film on a substrate. Further, there is a method in which an Au thin film or a solder plating material is arranged on a top surface of a terminal, in order to improve an electric contact between the terminal and wiring. There is also a method in which Ti or Pd is provided on a top surface of wiring, for preventing damages from plasma used in a semiconductor process.
Japanese Unexamined Patent Publication No. 152623/1997 (Tokukaihei 9-152623; published on Jun. 10, 1997) discloses a method for lowering a resistance of a leader terminal formed in a terminal section by forming a metallic light shielding film on a glass substrate. In the method, a metallic film for an auxiliary electrode is formed in advance so as to have substantially a same pattern as a pattern of the leader terminal. Then, the leader terminal is formed on the metallic film for the auxiliary electrode. Thus, it is possible to realize the lowering of the resistance of the leader terminal.
Further, Japanese Unexamined Patent Publication No. 2001-215526 (Tokukai 2001-215526; published on Aug. 10, 2001) discloses a method for forming a metallic film having a low resistance on an electrode terminal. The metallic film is made of noble metal. In the method, the metallic film is formed by depositing and aggregating the noble metal from a colloid solution containing the noble metal.
Further, Japanese Unexamined Patent Publication No. 120085/1997 (Tokukaihei 9-120085; published on May 6, 1997) discloses a method in which low resistance wiring (e.g. W) on a glass substrate is formed at the bottom of Ta wiring by carrying out a spattering method.
Further, Japanese Unexamined Patent Publication No. 97441/1999 (Tokukaihei 11-97441; published on Apr. 9, 1999) discloses a method in which (i) Cu wiring is formed in a groove on a silicon substrate, and (ii) a surface of the Cu wiring is polished and leveled.
In realization of peripheral wiring necessitating low resistance, when increasing a thickness of a metallic layer by using the foregoing conventional method such as the spattering method or the evaporation method, an entire thickness of matrix wiring increases, as described above. This is because the metallic layer is used as all the metallic layers for forming the matrix wiring such as signal lines and scanning lines.
The lowering of the resistance in the foregoing active matrix substrate does not necessarily have to be carried out with respect to the entire wiring on the active matrix substrate. In many cases, it is necessary for the lowering of resistance to be carried out only with respect to some wiring necessitating the low resistance. For example, in the foregoing example, it is necessary to lower the resistance of only a power supplying line for the driver element on the periphery of the active matrix substrate, and a grounding line.
Meanwhile, the wire may be damaged when the wire is in an environment during a step, i.e., in an environment that causes the wire to have an etching solution, an etching plasma atmosphere, a resist solution, a peeling solution, and the like. In view of the circumstances, the wiring is coated with a material having a resistance against such an environment. Note that this may not always be the case, i.e., not the entire wire is always damaged. In such a case, a partial coating may be enough.
However, a film formation, which is carried out by using a conventional spattering method or evaporation method, causes the metallic film for the wiring to be formed on the entire surface of the substrate. This results in an increase in the thicknesses of the signal lines and the scanning lines which do not necessitate low resistances. This further causes an interlayer insulation layer to have a poor coverage characteristic, so as not to uniformly cover the signal and scanning lines. Note that the interlayer insulation layer is an interlayer insulation layer in an overlap portion of the wiring lines, for example an interlayer insulation layer in a portion where a signal line and a scanning line intersect with each other. This may increase a possibility of defects such as short-circuiting of a wiring line and its upper layer. If nothing is done to the thickness of the upper layer, the upper layer may have a disconnection at its step portion. In order to avoid this problem, it becomes inevitably necessary to further increase the film thickness.
Further, a use of the spattering method or the evaporation method for increasing the thickness of the metallic film causes the metallic film to be easily peeled off when a stress is applied to the film. Moreover, the use of the spattering method or the evaporation method for increasing the thickness of the metallic film is disadvantageous in terms of cost. This is because, the same process has to be repeated, and a large amount of material cost is needed.
Further, in a case where a dry etching is carried out for patterning a thicken metallic film, it is necessary that resist remain longer than the time taken for the etching. This requires that the resist with sufficient thickness be formed. Alternatively, in a case of carrying out a wet etching, an increase in the thickness of the resist causes a poor circulation of etching liquid. This may cause a poor etching accuracy. Thus, patterning of the metallic film becomes difficult.
As described, in order to partially lower the resistance of the wiring, the metallic layer formed by the spattering method or evaporation method is used for increasing the film thickness. This method however influences a process time taken for process such as a film forming process, an etching process, or the like which is carried out with respect to the entire portion of the wiring. This causes deterioration in the productivity of a production line.
On the other hand, according to the foregoing Tokukaihei 9-152623 and Tokukai 2001-215526, the metallic film for the auxiliary electrode is formed at least a portion of the wiring, so that the resistance of the electrode terminal is lowered. However, the foregoing Tokukaihei 9-152623 and Tokukai 2001-215526 causes the following problems.
Firstly, in Tokukaihei 9-152623, the pattern of the metallic film for the auxiliary electrode is formed at the same time the metallic light shielding film is formed. This allows only a limited portion of the wiring (i.e., not the entire wiring) to have the low resistance by using the metallic film for the auxiliary electrode. Further, if the metallic film for the auxiliary electrode is formed by a spattering method or the like, the metallic film is formed in a wide range. Further, the number of photolithography process for patterning also increases. As described, it is extremely disadvantageous, in terms of cost, to carry out the photolithography process twice during a process of forming a single layer of wiring.
In Tokukai 2001-215526, an auxiliary metallic film is aggregated and deposited from the colloid solution of the noble metal by using Joule heat generated by passing an electric current. It is however presumed that the aggregation and deposition of the noble metal by using Joule heat is unfeasible. That is, an extremely large current is needed in order to generate such a Joule heat that is sufficiently high for causing deposition and aggregation of the noble metal. This extremely large current, if supplied to the wiring, may cause burning out of the wiring or other problems. Further, even if the method of Tokukai 2001-215526 allows a formation of the auxiliary metallic film with a small area like a terminal, the method is not suitable for forming the auxiliary metallic film having a large area like wiring or a pixel electrode.
Further, the method of Tokukai 2001-215526 has the following problems. Namely, with the method, the auxiliary metallic film can be formed only on a transparent conductive film. Further, since the colloid solution of the noble metal is applied on a substrate by using a spin coating method, the auxiliary metallic film is formed on the entire surface of the substrate. This causes an increase in the material cost for the noble metal colloid.
The above mentioned problems are true not only in terms of lowering the resistance, but also in terms of realizing the resistance against the process environment.